diff --git a/riscemu/__main__.py b/riscemu/__main__.py
index 3eac088..a03a0f9 100644
--- a/riscemu/__main__.py
+++ b/riscemu/__main__.py
@@ -1,7 +1,7 @@
 if __name__ == '__main__':
     from . import *
     from .helpers import *
-    from .instructions import RV32I, RVM
+    from .instructions import RV32I, RV32M
     import argparse
     import sys
 
@@ -61,7 +61,7 @@ if __name__ == '__main__':
     FMT_PRINT = FMT_BOLD + FMT_MAGENTA
 
     try:
-        cpu = CPU(cfg, [RV32I, RVM])
+        cpu = CPU(cfg, [RV32I, RV32M])
         loaded_exe = None
         for file in args.files:
             tk = cpu.get_tokenizer(RiscVInput.from_file(file))
diff --git a/riscemu/instructions/RVM.py b/riscemu/instructions/RV32M.py
similarity index 96%
rename from riscemu/instructions/RVM.py
rename to riscemu/instructions/RV32M.py
index 2a26586..91f3495 100644
--- a/riscemu/instructions/RVM.py
+++ b/riscemu/instructions/RV32M.py
@@ -2,7 +2,7 @@ from .InstructionSet import *
 from ..helpers import int_from_bytes, int_to_bytes, to_unsigned, to_signed
 
 
-class RVM(InstructionSet):
+class RV32M(InstructionSet):
     def instruction_mul(self, ins: 'LoadedInstruction'):
         INS_NOT_IMPLEMENTED(ins)
 
diff --git a/riscemu/instructions/__init__.py b/riscemu/instructions/__init__.py
index 55b5b97..819ba1c 100644
--- a/riscemu/instructions/__init__.py
+++ b/riscemu/instructions/__init__.py
@@ -1,3 +1,3 @@
 from .InstructionSet import InstructionSet
-from .RVM import RVM
-from .RV32I import RV32I
\ No newline at end of file
+from .RV32M import RV32M
+from .RV32I import RV32I