From 3033eb998549309dd5a24acfce545aa8a9c4b9dc Mon Sep 17 00:00:00 2001
From: Anton Lydike <me@antonlydike.de>
Date: Mon, 30 Aug 2021 20:10:22 +0200
Subject: [PATCH] tranlsation from absolute addressed to symbol-relative names
 for debugging

---
 riscemu/priv/ImageLoader.py | 12 +++++++++++-
 riscemu/priv/PrivMMU.py     |  2 ++
 riscemu/priv/PrivRV32I.py   |  8 +++-----
 3 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/riscemu/priv/ImageLoader.py b/riscemu/priv/ImageLoader.py
index 50cc25e..88c8f6b 100644
--- a/riscemu/priv/ImageLoader.py
+++ b/riscemu/priv/ImageLoader.py
@@ -98,7 +98,7 @@ class MemoryImageMMU(PrivMMU):
     @lru_cache(maxsize=32)
     def get_sec_containing(self, addr: int) -> Optional[LoadedMemorySection]:
         next_sec = len(self.data)
-        for sec_addr, name in sorted(self.debug_info['sections'].items(), key=lambda x: int(x[0]), reverse=True):
+        for sec_addr, name in reversed(self.debug_info['sections'].items()):
             if addr >= int(sec_addr):
                 owner, name = name.split(':')
                 base = int(sec_addr)
@@ -107,3 +107,13 @@ class MemoryImageMMU(PrivMMU):
                 return ElfLoadedMemorySection(name, base, size, self.data[base:next_sec], flags, owner)
             else:
                 next_sec = int(sec_addr)
+
+    def translate_address(self, addr: int):
+        sec = self.get_sec_containing(addr)
+        if sec.name == '.empty':
+            return "<empty>"
+        symbs = self.debug_info['symbols'][sec.owner]
+        for sym, val in reversed(symbs.items()):
+            if addr >= val:
+                return "{}{:+x} ({}:{})".format(sym, addr - val, sec.owner, sec.name)
+        return "{}:{}{:+x}".format(sec.owner, sec.name, addr - sec.base)
diff --git a/riscemu/priv/PrivMMU.py b/riscemu/priv/PrivMMU.py
index 39179f9..28f2ecf 100644
--- a/riscemu/priv/PrivMMU.py
+++ b/riscemu/priv/PrivMMU.py
@@ -19,6 +19,8 @@ class PrivMMU(MMU):
     def set_cpu(self, cpu: 'PrivCPU'):
         self.cpu = cpu
 
+    def translate_address(self, addr: int):
+        return ""
 
 class LoadedElfMMU(PrivMMU):
     def __init__(self, elf: ElfExecutable):
diff --git a/riscemu/priv/PrivRV32I.py b/riscemu/priv/PrivRV32I.py
index cc7c26b..ef56a75 100644
--- a/riscemu/priv/PrivRV32I.py
+++ b/riscemu/priv/PrivRV32I.py
@@ -81,12 +81,10 @@ class PrivRV32I(RV32I):
 
         sec = self.mmu.get_sec_containing(mepc)
         if sec is not None:
-            print(FMT_CPU + "[CPU] [{}] returning to mode: {} in binary {}, section {}, addr 0x{:x}".format(
+            print(FMT_CPU + "[CPU] [{}] returning to mode {} in {}".format(
                 self.cpu.cycle,
-                PrivModes(mpp),
-                sec.owner,
-                sec.name,
-                mepc
+                PrivModes(mpp).name,
+                self.mmu.translate_address(mepc)
             ) + FMT_NONE)
 
     def instruction_uret(self, ins: 'LoadedInstruction'):