From 254410e9ccc7db12b0f7414093e594912ddf7ca5 Mon Sep 17 00:00:00 2001 From: Anton Lydike Date: Sun, 27 Mar 2022 18:45:59 +0200 Subject: [PATCH] [priv] fixed error in halt csr --- riscemu/priv/PrivCPU.py | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/riscemu/priv/PrivCPU.py b/riscemu/priv/PrivCPU.py index d2481e2..f7df7a9 100644 --- a/riscemu/priv/PrivCPU.py +++ b/riscemu/priv/PrivCPU.py @@ -121,22 +121,18 @@ class PrivCPU(CPU): # CSR write callbacks: @self.csr.callback('halt') - def halt(old: int, new: int): + def halt(old: UInt32, new: UInt32): if new != 0: - self.exit = True - self.exit_code = new - - @self.csr.callback('mstatus') - def mstatus(old: int, new: int): - pass + self.halted = True + self.exit_code = new.value @self.csr.callback('mtimecmp') - def mtimecmp(old, new): + def mtimecmp(old: UInt32, new: UInt32): self._time_timecmp = (self.csr.get('mtimecmph') << 32) + new self._time_interrupt_enabled = True @self.csr.callback('mtimecmph') - def mtimecmph(old, new): + def mtimecmph(old: UInt32, new: UInt32): self._time_timecmp = (new << 32) + self.csr.get('mtimecmp') self._time_interrupt_enabled = True