diff --git a/riscemu/colors.py b/riscemu/colors.py
index 1ef85e8..6838a81 100644
--- a/riscemu/colors.py
+++ b/riscemu/colors.py
@@ -19,3 +19,4 @@ FMT_MEM = FMT_CYAN + FMT_BOLD
 FMT_PARSE = FMT_CYAN + FMT_BOLD
 FMT_CPU = FMT_BLUE + FMT_BOLD
 FMT_SYSCALL = FMT_YELLOW + FMT_BOLD
+FMT_DEBUG = FMT_MAGENTA + FMT_BOLD
diff --git a/riscemu/debug.py b/riscemu/debug.py
index 84e0e83..1681ef9 100644
--- a/riscemu/debug.py
+++ b/riscemu/debug.py
@@ -1,5 +1,7 @@
 import typing
 from .Registers import Registers
+from .colors import FMT_DEBUG, FMT_NONE
+
 if typing.TYPE_CHECKING:
     from . import *
 
@@ -42,5 +44,5 @@ def launch_debug_session(cpu: 'CPU', mmu: 'MMU', reg: 'Registers', prompt=""):
 
     readline.set_completer(rlcompleter.Completer(sess_vars).complete)
     readline.parse_and_bind("tab: complete")
-    code.InteractiveConsole(sess_vars).interact(banner=prompt, exitmsg="Exiting debugger")
+    code.InteractiveConsole(sess_vars).interact(banner=FMT_DEBUG + prompt + FMT_NONE, exitmsg="Exiting debugger")
     cpu.active_debug = False
diff --git a/riscemu/instructions/RV32I.py b/riscemu/instructions/RV32I.py
index 17a246a..7785716 100644
--- a/riscemu/instructions/RV32I.py
+++ b/riscemu/instructions/RV32I.py
@@ -1,6 +1,7 @@
 from .InstructionSet import *
 
 from ..helpers import int_from_bytes, int_to_bytes, to_unsigned, to_signed
+from ..colors import FMT_DEBUG, FMT_NONE
 
 
 class RV32I(InstructionSet):
@@ -280,9 +281,14 @@ class RV32I(InstructionSet):
     def instruction_sbreak(self, ins: 'LoadedInstruction'):
         ASSERT_LEN(ins.args, 0)
         if self.cpu.active_debug:
-            print("Debug instruction encountered at 0x{:08X}".format(self.pc-1))
+            print(FMT_DEBUG + "Debug instruction encountered at 0x{:08X}".format(self.pc-1) + FMT_NONE)
             raise LaunchDebuggerException()
-        launch_debug_session(self.cpu, self.mmu, self.regs, "Debug instruction encountered at 0x{:08X}".format(self.pc-1))
+        launch_debug_session(
+            self.cpu,
+            self.mmu,
+            self.regs,
+            "Debug instruction encountered at 0x{:08X}".format(self.pc-1)
+        )
 
     def instruction_nop(self, ins: 'LoadedInstruction'):
         ASSERT_LEN(ins.args, 0)