From 1b26497e4cd61156532b3bf6f6190a6ccfbcae32 Mon Sep 17 00:00:00 2001
From: Anton Lydike <me@antonlydike.de>
Date: Fri, 3 Feb 2023 16:45:29 +0000
Subject: [PATCH] base: add debug instructions

---
 examples/static-data.asm         | 20 ++++++++++++++++++++
 riscemu/IO/IOModule.py           |  4 ++--
 riscemu/instructions/RV_Debug.py | 19 +++++++++++++++++++
 riscemu/instructions/__init__.py |  3 ++-
 4 files changed, 43 insertions(+), 3 deletions(-)
 create mode 100644 examples/static-data.asm
 create mode 100644 riscemu/instructions/RV_Debug.py

diff --git a/examples/static-data.asm b/examples/static-data.asm
new file mode 100644
index 0000000..e521e35
--- /dev/null
+++ b/examples/static-data.asm
@@ -0,0 +1,20 @@
+.data
+my_data:
+.word   0x11223344, 0x55667788, 0x9900aabb, 0xccddeeff
+
+.text
+main:
+        // load base address into t0
+        la  t0, my_data
+        // begin loading words and printing them
+        lw  a0, 0(t0)
+        print.uhex a0
+        lw  a0, 4(t0)
+        print.uhex a0
+        lw  a0, 8(t0)
+        print.uhex a0
+        lw  a0, 12(t0)
+        print.uhex a0
+        // exit
+        li  a7, 93
+        ecall
\ No newline at end of file
diff --git a/riscemu/IO/IOModule.py b/riscemu/IO/IOModule.py
index 521ae93..883d00d 100644
--- a/riscemu/IO/IOModule.py
+++ b/riscemu/IO/IOModule.py
@@ -1,4 +1,4 @@
-from abc import ABC, abstractmethod
+from abc import ABC
 from typing import Optional
 
 from riscemu.types import MemorySection, MemoryFlags, T_RelativeAddress
@@ -19,4 +19,4 @@ class IOModule(MemorySection, ABC):
     def __repr__(self):
         return "{}[{}] at 0x{:0X} (size={}bytes, flags={})".format(
             self.__class__.__name__, self.name, self.base, self.size, self.flags
-        )
\ No newline at end of file
+        )
diff --git a/riscemu/instructions/RV_Debug.py b/riscemu/instructions/RV_Debug.py
new file mode 100644
index 0000000..1deeb9b
--- /dev/null
+++ b/riscemu/instructions/RV_Debug.py
@@ -0,0 +1,19 @@
+from .instruction_set import InstructionSet, Instruction
+
+
+class RV_Debug(InstructionSet):
+    def instruction_print(self, ins: Instruction):
+        reg = ins.get_reg(0)
+        print("register {} contains value {}".format(reg, self.regs.get(reg)))
+
+    def instruction_print_uint(self, ins: Instruction):
+        reg = ins.get_reg(0)
+        print("register {} contains value {}".format(reg, self.regs.get(reg).unsigned_value))
+
+    def instruction_print_hex(self, ins: Instruction):
+        reg = ins.get_reg(0)
+        print("register {} contains value {}".format(reg, hex(self.regs.get(reg))))
+
+    def instruction_print_uhex(self, ins: Instruction):
+        reg = ins.get_reg(0)
+        print("register {} contains value {}".format(reg, hex(self.regs.get(reg).unsigned_value)))
diff --git a/riscemu/instructions/__init__.py b/riscemu/instructions/__init__.py
index 3343ae8..45b5566 100644
--- a/riscemu/instructions/__init__.py
+++ b/riscemu/instructions/__init__.py
@@ -10,7 +10,8 @@ from .instruction_set import InstructionSet, Instruction
 from .RV32M import RV32M
 from .RV32I import RV32I
 from .RV32A import RV32A
+from .RV_Debug import RV_Debug
 
 InstructionSetDict = {
-    v.__name__: v for v in [RV32I, RV32M, RV32A]
+    v.__name__: v for v in [RV32I, RV32M, RV32A, RV_Debug]
 }