From 157589548d7381fa073952d1e896f42176cd1ba4 Mon Sep 17 00:00:00 2001 From: Anton Lydike Date: Mon, 19 Apr 2021 00:04:51 +0200 Subject: [PATCH] unified instruction parsing code --- riscemu/instructions/InstructionSet.py | 15 +++++++++++++++ riscemu/instructions/RV32I.py | 17 +++++++---------- 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/riscemu/instructions/InstructionSet.py b/riscemu/instructions/InstructionSet.py index e4ca7e3..e52b453 100644 --- a/riscemu/instructions/InstructionSet.py +++ b/riscemu/instructions/InstructionSet.py @@ -30,6 +30,21 @@ class InstructionSet(ABC): def parse_mem_ins(self, ins: 'LoadedInstruction'): return self.cpu.parse_mem_ins(ins) + def parse_rd_rs_rs(self, ins: 'LoadedInstruction'): + ASSERT_LEN(ins.args, 3) + return ins.get_reg(0), self.get_reg_content(ins, 1), self.get_reg_content(ins, 2) + + def parse_rd_rs_imm(self, ins: 'LoadedInstruction'): + ASSERT_LEN(ins.args, 3) + return ins.get_reg(0), self.get_reg_content(ins, 1), ins.get_imm(2) + + def get_reg_content(self, ins: 'LoadedInstruction', ind: int): + """ + get the register name from ins and then return the register contents + """ + return self.regs.get(ins.get_reg(ind)) + + @property def pc(self): return self.cpu.pc diff --git a/riscemu/instructions/RV32I.py b/riscemu/instructions/RV32I.py index 1d99848..82ca515 100644 --- a/riscemu/instructions/RV32I.py +++ b/riscemu/instructions/RV32I.py @@ -226,24 +226,24 @@ class RV32I(InstructionSet): def instruction_bge(self, ins: 'LoadedInstruction'): ASSERT_LEN(ins.args, 3) - reg1 = self.get_reg(ins, 0) - reg2 = self.get_reg(ins, 1) - dest = self.get_reg(ins, 2) + reg1 = self.get_reg_content(ins, 0) + reg2 = self.get_reg_content(ins, 1) + dest = ins.get_imm(2) if reg1 >= reg2: self.pc = dest def instruction_bltu(self, ins: 'LoadedInstruction'): ASSERT_LEN(ins.args, 3) - reg1 = self.get_reg(ins, 0) - reg2 = self.get_reg(ins, 1) + reg1 = self.get_reg_content(ins, 0) + reg2 = self.get_reg_content(ins, 1) dest = ins.get_imm(2) if to_unsigned(reg1) < to_unsigned(reg2): self.pc = dest def instruction_bgeu(self, ins: 'LoadedInstruction'): ASSERT_LEN(ins.args, 3) - reg1 = to_unsigned(self.get_reg(ins, 0)) - reg2 = to_unsigned(self.get_reg(ins, 1)) + reg1 = to_unsigned(self.get_reg_content(ins, 0)) + reg2 = to_unsigned(self.get_reg_content(ins, 1)) dest = ins.get_imm(2) if reg1 >= reg2: self.pc = dest @@ -292,6 +292,3 @@ class RV32I(InstructionSet): def instruction_nop(self, ins: 'LoadedInstruction'): pass - - def get_reg(self, ins: 'LoadedInstruction', ind: int): - return self.regs.get(ins.get_reg(ind))