added add_accept_imm option flag to allow add rd, rs, imm instructions

README.md

@@ -45,6 +45,7 @@ OPTIONS and SYSCALL_OPTIONS is a list of comma-separated flags that will be enab
 disable_debug           Disable the ebreak and sbreak instructions
 no_syscall_symbols      Don't make syscall symbols globally available
 fail_on_ex              Do not launch an interactive debugger when the CPU loop catches an exception
+add_accept_imm          accept "add rd, rs, imm" instructions, even though they are not standard
 
 --syscall-opts SYSCALL_OPTS: (-so)
                         Options to control syscall behaviour
@@ -72,6 +73,8 @@ See [docs/debugging.md](docs/debugging.md) for more info.
   * RISC-V reference card: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf
   
 ## TODO:
+ * Currently registers don't enforce 32 bit (no overflows etc)
+ * Correctly handle 12 and 20 bit immediate (currently not limited to bits at all)
  * Add a cycle limit to the options and CPU to catch infinite loops
  * Move away from `print` and use `logging.logger` instead
  * Properly support stack/heap

riscemu/Config.py

@@ -6,6 +6,7 @@ from typing import Optional
 class RunConfig:
     preffered_stack_size: Optional[int] = None
     include_scall_symbols: bool = True
+    add_accept_imm: bool = False
     # debugging
     debug_instruction: bool = True
     debug_on_exception: bool = True

riscemu/__main__.py

@@ -44,7 +44,7 @@ if __name__ == '__main__':
                         help='The assembly files to load, the last one will be run')
 
     parser.add_argument('--options', '-o', action=OptionStringAction,
-                        keys=('disable_debug', 'no_syscall_symbols', 'fail_on_ex'))
+                        keys=('disable_debug', 'no_syscall_symbols', 'fail_on_ex', 'add_accept_imm'))
 
     parser.add_argument('--syscall-opts', '-so', action=OptionStringAction,
                         keys=('fs_access', 'disable_input'))
@@ -63,6 +63,7 @@ if __name__ == '__main__':
         debug_instruction=not args.options['disable_debug'],
         include_scall_symbols=not args.options['no_syscall_symbols'],
         debug_on_exception=not args.options['fail_on_ex'],
+        add_accept_imm=args.options['add_accept_imm'],
         scall_fs=args.syscall_opts['fs_access'],
         scall_input=not args.syscall_opts['disable_input']
     )

riscemu/instructions/RV32I.py

@@ -97,7 +97,15 @@ class RV32I(InstructionSet):
         )
 
     def instruction_add(self, ins: 'LoadedInstruction'):
-        dst, rs1, rs2 = self.parse_rd_rs_rs(ins)
+        dst = ""
+        if self.cpu.conf.add_accept_imm:
+            try:
+                dst, rs1, rs2 = self.parse_rd_rs_imm(ins)
+            except:
+                pass
+        if not dst:
+            dst, rs1, rs2 = self.parse_rd_rs_rs(ins)
+
         self.regs.set(
             dst,
             rs1 + rs2