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# RISC-V (userspace) emulator in python
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Implementing a basic RISC-V emulator, aimed at being easily extendable.
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Currently supported (but not implemented) instructions:
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````
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lb, lh, lw, lbu, lhu, sb, sh, sw, sll, slli, srl, srli, sra,
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srai, add, addi, sub, lui, auipc, xor, xori, or, ori, and,
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andi, slt, slti, sltu, sltiu, beq, bne, blt, bge, bltu, bgeu,
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j, jr, jal, jalr, ret, scall, break, nop
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````
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See the docs on [asembly](docs/assembly.md) and [the cpu](docs/CPU.md) for more detail.
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Currently, symbols (such as `main:`) are looked-up in runtime. This allows for better debugging, I believe.
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Basic IO should work, as open, read, write and close are supported for stdin/stdout/stderr and even aribtrary file paths (if enabled)
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## Resources:
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* Pseudo ops: https://www.codetd.com/article/8981522
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* RISC-V reference card: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf
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## TODO:
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* add global symbol lookup table
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* better pseudo-ops
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* mmu inspect methods
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