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14 lines
597 B
Markdown
14 lines
597 B
Markdown
4 years ago
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# The CPU
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The CPU emulates some RISC-V instructions:
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* all loads/stores: `lb, lh, lw, lbu, lhu, sw, sh, sb`
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* supported arg format is either `rd, imm(reg)` or `reg, reg, imm`
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* all branch statements: `beq, bne, blt, bge, bltu, bgeu`
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* all jumps `j, jal, jalr, ret`
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* basic arithmetic: `add, addi, sub` (not `lui, auipc`)
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* shifts: `sll, slli, srl, srli, sra, srai`
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* `scall, ecall, sbreak, ebreak` (both `s` and `e` version are the same instrcution)
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* compares (non immediate): `slt, sltu`, not `slti, sltiu`
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* logiacl (non immediate): `and, or, xor` not (`andi, ori, xori`)
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