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42 lines
2.2 KiB
Markdown
42 lines
2.2 KiB
Markdown
4 years ago
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# RiscV (userspace) emulator in python
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Implementing a basic RISC-V emulator, aimed at being easily extendable.
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Currently supported (but not implemented) instructions:
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````
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lb, lh, lw, lbu, lhu, sb, sh, sw, sll, slli, srl, srli, sra,
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srai, add, addi, sub, lui, auipc, xor, xori, or, ori, and,
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andi, slt, slti, sltu, sltiu, beq, bne, blt, bge, bltu, bgeu,
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j, jr, jal, jalr, ret, scall, break, nop
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````
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Current register implementation (should be all standard userspace registers):
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```
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Registers[read,written](
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zero=0x00000000 ra =0x00000000 sp =0x00000000 gp =0x00000000 tp =0x00000000 fp =0x00000000
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--------------- --------------- --------------- --------------- --------------- ---------------
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a0 =0x00000000 s0 =0x00000000 t0 =0x00000000 ft0 =0x00000000 fa0 =0x00000000 fs0 =0x00000000
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a1 =0x00000000 s1 =0x00000000 t1 =0x00000000 ft1 =0x00000000 fa1 =0x00000000 fs1 =0x00000000
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a2 =0x00000000 s2 =0x00000000 t2 =0x00000000 ft2 =0x00000000 fa2 =0x00000000 fs2 =0x00000000
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a3 =0x00000000 s3 =0x00000000 t3 =0x00000000 ft3 =0x00000000 fa3 =0x00000000 fs3 =0x00000000
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a4 =0x00000000 s4 =0x00000000 t4 =0x00000000 ft4 =0x00000000 fa4 =0x00000000 fs4 =0x00000000
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a5 =0x00000000 s5 =0x00000000 t5 =0x00000000 ft5 =0x00000000 fa5 =0x00000000 fs5 =0x00000000
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a6 =0x00000000 s6 =0x00000000 t6 =0x00000000 ft6 =0x00000000 fa6 =0x00000000 fs6 =0x00000000
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a7 =0x00000000 s7 =0x00000000 ft7 =0x00000000 fa7 =0x00000000 fs7 =0x00000000
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s8 =0x00000000 fs8 =0x00000000
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s9 =0x00000000 fs9 =0x00000000
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s10 =0x00000000 fs10=0x00000000
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s11 =0x00000000 fs11=0x00000000
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)
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```
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Current pseudo ops:
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```
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.align, .ascii, .asciiz, .byte, .data, .double, .extern,
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.float, .globl, .half, .kdata, .ktext, .set, .space, .text, .word
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```
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## Resources:
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* Pseudo ops: https://www.codetd.com/article/8981522
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