From b2dab6cb371357dbc09bb4d09c330de7cb6ab209 Mon Sep 17 00:00:00 2001 From: Anton Lydike Date: Fri, 16 Jul 2021 22:26:55 +0200 Subject: [PATCH] added config options to makefile - now able to build various variations --- Makefile | 27 ++++++++++++++++++++++----- kinclude/boot.S | 26 +++++++++++++++----------- kinclude/csr.c | 6 +++--- kinclude/csr.h | 7 ++++++- 4 files changed, 46 insertions(+), 20 deletions(-) diff --git a/Makefile b/Makefile index adf7c3b..2bd326b 100644 --- a/Makefile +++ b/Makefile @@ -12,8 +12,23 @@ GCC_PREF=riscv32-unknown-elf- CC=$(GCC_PREF)gcc OBJDUMP=$(GCC_PREF)objdump -CFLAGS=-I$(KLIBDIR) -march=rv32im -O3 +CFLAGS=-I$(KLIBDIR) -O3 -MD KERNEL_CFLAGS=-nostdlib -T linker.ld +ARCH = rv32im + +### Build configuration: + +# uncomment to build with only the rv32i standard +CFLAGS += -D__risc_no_ext=1 +ARCH = rv32i + +# configure if mtime is memory-mapped or inside a CSR: +# replace 0xFF11FF22FF33 with the correct address +CFLAGS += -DTIMECMP_IN_MEMORY=1 -DTIMECMP_MEM_ADDR=0xFF11FF22 + + +### End configuration +CFLAGS += -march=$(ARCH) # dependencies that need to be built: _DEPS = ecall.c csr.c mutex.c sched.c @@ -26,10 +41,10 @@ DEPS = $(patsubst %,$(KLIBDIR)/%,$(_DEPS)) OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ)) -$(ODIR)/boot.o: - $(CC) -c -o $@ $(KLIBDIR)/boot.S $(CFLAGS) +$(ODIR)/boot.o: $(KLIBDIR)/boot.S + $(CC) -c -o $@ $(KLIBDIR)/boot.S $(CFLAGS) -D__assembly=1 -$(ODIR)/%.o: +$(ODIR)/%.o: $(KLIBDIR)/%.c $(KLIBDIR)/%.h $(CC) -c -o $@ $(KLIBDIR)/$*.c $(CFLAGS) kernel: $(OBJ) @@ -42,4 +57,6 @@ kernel-dump: kernel .PHONY: clean clean: - rm -rf $(ODIR) *~ $(KLIBDIR)/*~ $(TARGET) \ No newline at end of file + rm -rf $(ODIR) *~ $(KLIBDIR)/*~ $(TARGET) + +-include $(OBJ:.o=.d) \ No newline at end of file diff --git a/kinclude/boot.S b/kinclude/boot.S index f42b1e9..cc7cf76 100644 --- a/kinclude/boot.S +++ b/kinclude/boot.S @@ -1,3 +1,4 @@ +#include "csr.h" .section .stack stack_bottom: @@ -9,11 +10,11 @@ stack_top: // Set up all the CSR mstatus_offsets -.set mstatus, 0x300 // machine status -.set mscratch, 0x340 -.set mtvec, 0x305 // machine trap handler -.set mcause, 0x342 // machine trap cause -.set mtval, 0x343 // machine bad address or instruction +// .set mstatus, 0x300 // machine status +// .set mscratch, 0x340 +// .set mtvec, 0x305 // machine trap handler +// .set mcause, 0x342 // machine trap cause +// .set mtval, 0x343 // machine bad address or instruction // .set misa, 0x301 // machine ISA // .set mie, 0x304 // machine interrupt enable // .set mip, 0x344 // machine interrupt pending @@ -30,7 +31,7 @@ _start: // setup a0 to hold |trap tbl addr|mode| // len:| 30 | 2 | la a0, trap_vector - csrrw zero, mtvec, a0 // write a0 into mtvec csr entry + csrrw zero, CSR_MTVEC, a0 // write a0 into mtvec csr entry // enable interrupts in mstatus // this is the setting loaded: // [07] MPIE = 1 - we want to enable interrupts with mret @@ -38,7 +39,7 @@ _start: // [11:12] MPP = 0 - we want to return into user mode // all other bits should be zero li a0, 0x80 - csrrw zero, mstatus, a0 // write to mstatus + csrrw zero, CSR_MSTATUS, a0 // write to mstatus // write .option push .option norelax @@ -56,7 +57,7 @@ _start: jal init // halt machine after returning from init - csrwi 0x789, 1 + csrwi CSR_HALT, 1 1: j 1b @@ -119,8 +120,8 @@ trap_vector: // (numbytes) when we reach the blt instruction for the first time. // this math works so good, because we write 4 bytes of mem, in 4 bytes of // instructions. Therefore instruction bytes to skip = write bytes to skip -memset: // bytes to skip = numbytes - ((a2 - a1) % numbytes) +memset: sub t1, a2, a1 // t1 = a2 - a1 li t2, 32 // = numbytes rem t1, t1, t2 // t1 = (a2 - a1) % numbytes @@ -130,9 +131,11 @@ memset: sub a1, a1, t2 // subtract skipped bytes from a2 // to account for the skipped instruction // when we reach the addi, a1, a1, 32 inst. - auipc t1, 0 // calc jump + auipc t1, 0 // get current address add t1, t2, t1 // add calulated offset jalr zero, t1, 12 // skip the instructions by forward-jumping + // the 12 is added to compensate for the + // three instructions auipc, add, jalr 1: sw a0, 0(a1) sw a0, 4(a1) @@ -144,4 +147,5 @@ memset: sw a0, 28(a1) addi a1, a1, 32 blt a1, a2, 1b - ret \ No newline at end of file + ret +#endif \ No newline at end of file diff --git a/kinclude/csr.c b/kinclude/csr.c index 9bc459c..bd8cf2a 100644 --- a/kinclude/csr.c +++ b/kinclude/csr.c @@ -6,9 +6,9 @@ void write_mtimecmp(unsigned long long int mtimecmp) { unsigned int lower = mtimecmp; unsigned int higher = mtimecmp >> 32; __asm__( - "sw %2, %0\n" - "sw %3, %1" :: - "I"(TIMECMP_MEM_ADDR),"I"(TIMECMP_MEM_ADDR + 4), + "sw %1, 0(%0)\n" + "sw %2, 4(%0)" :: + "r"(TIMECMP_MEM_ADDR), "r"(lower), "r"(higher) ); } diff --git a/kinclude/csr.h b/kinclude/csr.h index 3531b7b..567eef9 100644 --- a/kinclude/csr.h +++ b/kinclude/csr.h @@ -16,9 +16,12 @@ #define CSR_MTIMECMP 0x780 // mtimecmp register for timer interrupts #define CSR_MTIMECMPH 0x781 // mtimecmph register for timer interrupts +#ifndef CSR_HALT #define CSR_HALT 0x789 // writing nonzero value here will halt the cpu +#endif -#define TIMECMP_MEM_ADDR 0xffff +// do not define C macros and other C stuff when this is included inside assembly +#ifndef __assembly #define CSR_READ(csr_id, result) {\ __asm__ ("csrr %0, %1" : "=r"((result)) : "I"((csr_id))); \ @@ -35,4 +38,6 @@ void write_mtimecmp(unsigned long long int mtimecmp); unsigned long long int read_time(); +#endif + #endif \ No newline at end of file